The present invention generally relates to the field of computer aided data analysis and, in particular, to the highly specialized computers capable of processing two dimensionally structured data sets, generally referred to as images, that are known as Cellular Array Processors (CAP).
In the field of image processing, the Cellular Array Processor is generally well-known as a type of computer system whose architecture is particularly suited for the task of image processing. Although the specific design may differ substantially between different implementations, the general architecture of the Cellular Array Processor is quite distinctive. Typically, a system will include a highly specialized array processor that is controlled by a control processor of conventional design. The array processor, in turn, is formed from a large number of elemental processors that are distributed as individual cells within a regular matrix. (This gives rise to the descriptive name "Cellular Array Processor".)
The elemental processors are essentially identical and generally contain a function-programmable logic circuit and memory register. The programmable logic circuit is typically capable of selectively performing a limited number of primitive logic and arithmetic functions, such as "and", "or", "invert", and "rotate" on the data stored in its respective memory register in conjunction with data provided by the control processor. The control processor is linked to the elemental processors via a common instruction bus. Thus, all of the elemental processors operate separately, yet synchronously, in the performance of a common logical function on the data contained in their respective memory registers. (This is commonly referred to as Single Instruction, Multiple Data, or SIMD operation.)
Cellular Array Processor systems are particularly well suited for image processing applications, since the memory registers present in the cellular array permit the digital representation of the image to be mapped directly into the processor. Thus, the spatial interrelationship of the data within the two-dimensionally structured data set is intrinsically preserved. By directing the array processor to perform a selected sequence of SIMD logical operations corresponding to the performance of a desired image processing algorithm, the data at every point in the image can be processed essentially in parallel.
In order to process an image, it is necessary to convert that image into electrical signals suitable for processing by the CAP. While conventional video cameras are generally used to convert images to electrical signals, their conversion rate is substantially slower than the CAP processing time. This is so because video cameras generally process image information serially, as opposed to the parallel processing capability of the CAP.
Accordingly, it is an object of the present invention to provide high speed conversion of an image to digital signals.
It is another object of the present invention to provide apparatus for high speed analog to digital conversion of two-dimensional information.